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fn7832 rev 1.00 page 1 of 36 july 13, 2012 fn7832 rev 1.00 july 13, 2012 zl8101 adaptive digital dc/dc pwm cont roller with auto compensation datasheet the zl8101 is a digital pwm controller with auto compensation that is designed to work with either the zl1505 mosfet driver ic, isl6611 phas e doubler ic, or drmos type devices. current sharing allows multiple devices to be connected in parallel to source loads with very high current demands. adaptive performanc e optimization algorithms improve power conversion efficiency across the entire load range. zilker labs digital-dc? technology enables a blend of power conversion performance and power management features. the zl8101 is designed to be a flexible building block for dc power and can be easily adapted to designs ranging from a single-phase power su pply operating from a 4.5v input to a multi-phase supply operating from a 12v input. the zl8101 eliminates the need for complicated power supply managers as well as numerous external discrete components. most operating features can be configured by simple pin-strap/resistor selection or through the smbus? serial interface. the zl8101 uses the pmbus? protocol for communication with a host cont roller and the digital-dc bus for communication between other zilker labs devices. features ? efficient synchronous buck controller ? adaptive performance optimization algorithms ? 1% output voltage accuracy ? auto compensation ? snapshot? parametric capture ?i 2 c/smbus interface, pmbus compatible ? internal non-volatile memory (nvm) ? tri-state pwm gate outputs ? compatible with industry standard drmos devices ? compatible with intersil isl6611 phase doubler ? synchronized external driver control applications ? servers/storage equipment ? telecom/datacom equipment ? power supplies (memory, dsp, asic, fpga) related literature ? an2033 ?zilker labs pmbus command set - ddc products? ? an2034 ?configuring current sharing on the zl2004 and zl2006? ? an2010 ?thermal and layout guidelines for digital-dc? products? figure 1. efficiency vs load current output current (a) efficiency (%) 76 81 86 91 96 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 v in = 12v l = 0.45h g h = 1 x bsc050ne2ls g l = 2 x bsc010ne2ls v out = 3.3v v out = 1.0v v out = 1.5v v out = 1.2v v out = 1.8v v out = 2.5v f sw = 400khz
zl8101 fn7832 rev 1.00 page 2 of 36 july 13, 2012 block diagram zl types current sense ldo temp sensor v (0, 1) vmon mgn vr vdd pwml isena isenb level shifter xtemp pwm i 2 c scl sda salrt sa (0,1) en pg ss fc monitor controller v25 sync sgnd dgnd adc non- volatile memory vtrk vsen ddc pwmh power management drvctl part number (notes 1, 2) part marking temp. range (c) pack method package pkg. dwg. # zl8101alaft 8101 -40 to +85 tape and reel 6k 32 ld qfn l32.5x5g ZL8101ALAFTK 8101 -40 to +85 tape and reel 1k 32 ld qfn l32.5x5g zl8101alaf 8101 -40 to +85 bulk 32 ld qfn l32.5x5g notes: 1. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requir ements of ipc/jedec j std-020. 2. for moisture sensitivity level (msl), please see device information page for zl8101 . for more information on msl please see techbrief tb363 . l -cc s bbbbb p zl f t zl = zilker labs designator base part number 5 character max. package designator a: (qfn) operating temperature range l: (-40c to +85c) z: (-55c to +125c) k: (0 to +70c) j: (0c to +85c) firmware revision any alphanumeric character lead finish f (lead-free matte tin) n (lead-free nipdau) shipping option t3: (tape and reel - 3000 piece) t4: (tape and reel - 4000 piece) t1 or tk: (tape and reel - 1000 piece) j: (trays) t5: (tape and reel - 5000 piece) w: (waffle pack) custom code any alphanumeric character t: (tape and reel - 100 piece for t6: (tape and reel - 6000 piece) zilker legacy products) t: (tape and reel - full reel qty. for intersil zilker products)
zl8101 fn7832 rev 1.00 page 3 of 36 july 13, 2012 pin configuration zl8101 (32 ld qfn) top view pg ss en nc mgn ddc xtemp v25 fc v0 v1 vmon vtrk vsen+ vsen- dgnd sync sa0 sa1 nc scl sda salrt vdd vr pwmh sgnd pwml isena isenb nc 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 exposed paddle* *connect to sgnd drvctl pin descriptions pin label type (note 3) description 1 dgnd pwr digital ground. connect to low impedance contiguous ground plane. 2synci/o, m (note 4) clock synchronization input. used to set the frequency of the internal switch clock, to sync to an external clock or to output internal clock. 3sa0 i, m serial address select pins. used to assign a unique a ddress for each individual de vice or to enable certain management features. 4sa1 5 nc no connect. leave pin open. 6 scl i/o serial clock. connect to external host and/or to other zl devices. 7 sda i/o serial data. connect to external host and/or to other zl devices. 8 salrt o serial alert. connect to external host if desired. 9 fc i auto compensation configuration pi n. used to set up auto compensation. 10 v0 i, m output voltage selection pins. used to set v out set-point and v out max. 11 v1 12 vmon i, m external voltage monitoring (can be used for external driver bias monitoring for power-good). 13 drvctl o external driver enable control output. 14 vtrk i tracking sense input. used to track an external voltage source. 15 vsen+ i differential output voltage sense feedback . connect to positive output regulation point. 16 vsen- i differential output voltage sense feedback. connect to negative output regulation point. 17 nc no connect. leave pin open. 18 isenb i differential voltage input for current sensing. 19 isena i differential voltage input for current sensing. high voltage (dcr).
zl8101 fn7832 rev 1.00 page 4 of 36 july 13, 2012 20 pwml o pwm gate low signal. 21 sgnd pwr connect to low impedance ground plane. internal connection to sgnd. 22 pwmh o pwm gate high signal. 23 vr pwr internal 5v reference. 24 vdd (note 5) pwr supply voltage. 25 v25 pwr internal 2.5v reference used to power internal circuitry. 26 xtemp i external temperature sensor input. co nnect to external 2n3904 (base emitter junction). 27 ddc i single wire ddc bus (current sh aring, inter device communication). 28 mgn i v out margin control. 29 nc no connect. leave pin open. 30 en i enable. active signal enables pwm switching. 31 ss i, m soft-start delay and ramp select. sets the delay from when en is asserted until the output voltage starts to ramp and the ramp time. 32 pg o power-good output. pd sgnd pwr exposed thermal pad. connect to low impeda nce ground plane. internal connection to sgnd. notes: 3. i = input, o = output, pwr = power or ground. m = mult i-mode pins (refer to ?multi-mode pins? on page 12). 4. the sync pin can be used as a logic pin, a clock input or a clock output. 5. the v dd pin voltage is used to measure v in as part of the pre-bias calculation and loop gain calculation used for current sharing ramps. pin descriptions (continued) pin label type (note 3) description
zl8101 fn7832 rev 1.00 page 5 of 36 july 13, 2012 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 zl8101 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 digital-dc architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power conversion overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 multi-mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power conversion functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 internal bias regulators and input supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 start-up procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power train component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 current limit threshold selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 non-linear response (nlr ) settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 efficiency optimized driver dead-time cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 adaptive diode emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 power management functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 input undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 output pre-bias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 minimum duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 voltage tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 tracking with autocomp enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 current sharing and tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 configuring tracking groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 voltage margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 external voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 i2c/smbus communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 i2c/smbus device address selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 active current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 turn-on/off ramp behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 current share fault behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 phase adding/dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 monitoring via i2c/smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 temperature monitoring using the xtemp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 snapshot? parameter capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 non-volatile memory and device security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 configuration files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 programmable gain amplifier bias current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 package outline drawing . . . . . . . . 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zl8101 fn7832 rev 1.00 page 6 of 36 july 13, 2012 absolute maximum ratings (note 6) thermal information dc supply voltage for vdd pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v logic i/o voltage for ddc, en, fc, mgn, pg, sa(0,1), salrt, scl, sda, ss, sync, vmon, v(0,1) pins . . . . . . . . . . . -0.3v to 6.5v analog input voltages for vsen+, vsen-, vtrk, xtemp pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v analog input voltages for isena, isenb pins . . . . . . . . . . . . . -1.5v to 6.5v mosfet drive reference for vr pin. . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v logic reference for v25 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3v ground voltage differential (v dgnd -v sgnd ) for dgnd, sgnd pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 2000v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v latch up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tested per jesd-78 thermal resistance (typical) ? ja (c/w) ? jc (c/w) 32 ld qfn package (notes 7, 8) . . . . . . . . . . . 35 5 operating junction temperature range. . . . . . . . . . . . . . . . . .-40c to +125c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions input supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 14v output voltage range (inductor sensing) (note 9) . . . . . . . . . 0.54v to 4v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. voltage measured with respect to sgnd. 7. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 8. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 9. includes margin limits. electrical specifications v dd = 12v, t a = -40c to +85c, unless otherwise sp ecified. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter conditions min (note 10) typ max (note 10) unit input and supply characteristics i dd supply current at f sw = 200khz gh no load, gl no load, misc_config[7] = 1 16 30 ma i dd supply current at f sw = 1.4mhz 25 50 ma i dds shutdown current en = 0v, no i 2 c/smbus activity 6.5 8 ma vr reference output voltage v dd > 6v 4.5 5.2 5.7 v v25 reference output voltage v r > 3v 2.25 2.5 2.75 v output characteristics output voltage adjustment range (note 11) 0.6 3.6 v output voltage set-point resolution set using resistors 10 mv set using i 2 c/smbus 0.025 % fs (note 12) output voltage accuracy (note 13) includes line, load, temp - 1 1 % vsen input bias current vsen = 4v 80 150 a current sense differential input voltage (v out referenced) v isena - v isenb - 50 50 mv current sense input bias current (v out referenced, v out ? 3.6v) isena - 50 50 na isenb - 75 75 a soft-start delay duration range set using ss pin or resistor 220 ms set using i 2 c/smbus 0.002 500 s soft-start delay duration accuracy turn-on delay (precise mode) (notes 14, 15) 0.25 ms turn-on delay (normal mode) (note 16) -1/+5 ms turn-off delay (note 16) -1/+5 ms
zl8101 fn7832 rev 1.00 page 7 of 36 july 13, 2012 soft-start ramp duration range set using ss pin or resistor 220 ms set using i 2 c 0 200 ms soft-start ramp duration accuracy 100 s logic input/output characteristics logic input bias current en, pg, scl, sda, salrt pins - 250 250 na mgn input bias current - 1 1 ma logic input low, v il 0.8 v logic input open (n/c) m ulti-mode logic pins 1.4 v logic input high, v ih 2.0 v logic output low, v ol i ol ? 4ma 0.4 v logic output high, v oh i oh ? -2ma 2.25 v pwm outputs (pwmh, pwml) pwm output voltage low threshold i load = 500a (note 20) sinking 100 mv pwn output voltage high threshold 4.7 v external driver control (drvctl) hw_en to drvctl delay (td ed ) turn-on 100 350 s 3s_delay turn-off 0.1 2 ms td off turn-off 0.1 0.5 ms oscillator and switching characteristics switching frequency range 200 1400 khz switching frequency set-point accuracy -5 5 % maximum pwm duty cycle factory default, decreases with frequency 95 % minimum sync pulse width 150 ns input clock frequency drift tolerance external clock source - 13 13 % tracking vtrk input bias current vtrk = 4.0v 110 200 a vtrk tracking ramp accuracy 100% tracking, v out - vtrk (during ramps) -100 +100 mv vtrk regulation accuracy 100% tracking, v out - vtrk (steady state) 1.5% % fault protection characteristics uvlo threshold range configurable via i 2 c/smbus 2.85 16 v uvlo set-point accuracy -150 150 mv uvlo hysteresis factory default 3 % configurable via i 2 c/smbus 0100 % uvlo delay 2.5 s power-good v out low threshold factory default 90 % v out power-good v out high threshold factory default 115 % v out power-good v out hysteresis factory default 5 % electrical specifications v dd = 12v, t a = -40c to +85c, unless otherwise sp ecified. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 10) typ max (note 10) unit
zl8101 fn7832 rev 1.00 page 8 of 36 july 13, 2012 power-good delay using pin-strap or resistor (note 17) 220 ms configurable via i 2 c/smbus 0 500 s vsen undervoltage threshold factory default 85 % v out configurable via i 2 c/smbus 0110 % v out vsen overvoltage threshold factory default 115 % v out configurable via i 2 c/smbus 0 115 % v out vsen undervoltage hysteresis 5% v out vsen undervoltage/overvoltage fault response time factory default 16 s configurable via i 2 c/smbus 560 s current limit set-point accuracy (v out referenced) 10 % fs (note 18) current limit protection delay factory default 5 t sw (note 19) configurable via i 2 c/smbus 132 t sw (note 19) temperature compensation of current limit protection threshold factory default 4400 ppm/c configurable via i 2 c/smbus 100 12700 ppm/c thermal protection threshold (junction temperature) factory default 125 c configurable via i 2 c/smbus -40 125 c thermal protection hysteresis 15 c notes: 10. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11. set point adjustment range does not include margin limits. 12. percentage of full scale (fs) with temperature compensation applied. 13. v out set-point measured at the terminatio n of the vsen+ and vsen- sense points. 14. the device requires approximately 2ms following an enable si gnal and prior to ramping its output. the delay accuracy will va ry by 0.25ms around the 2ms minimum delay value. 15. precise ramp timing mode is only valid when using en pin to enable the device rather than pmbus enable. 16. the devices may require up to a 4ms delay following an assert ion of the enable signal (normal mode) or following the de-asse rtion of the enable signal. 17. factory default power-good delay is set to the same value as the soft-start ramp time. 18. percentage of full scale (fs) with temperature compensation applied. 19. t sw = 1/f sw , where f sw is the switching frequency. 20. outputs are tri-state when disabled. electrical specifications v dd = 12v, t a = -40c to +85c, unless otherwise sp ecified. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 10) typ max (note 10) unit
fn7832 rev 1.00 page 9 of 36 july 13, 2012 zl8101 figure 2. example design us ing zl8101 and zl1505 driver note: 21. the ddc bus requires a pull-up resistor. the resistance will vary based on the capacitive loading of the bus (and on the num ber of devices connected). the 10k default value, assuming a maximum of 100pf per device, provides the necessary 1s pull-up rise time. please refer to the ?digital-dc bus? section on page 30 for m ore information. vout c5 fb+ fb- c4 bst q1 u1 zl1505 hsel 1 gh 2 sw 3 pwmh 4 pwml 5 lsel 6 gnd 7 gl 8 vdd 9 bst 10 epad 11 vin = 4.5v-14v vdrv = 4.5v-6.5v sw isenb c9 10f c2 4.7f c7 0.01f isena pwml ddc c3 pg r3 6.65k sgnd scl r1 100k en sda fb1 sgnd sgnd pwmh c8 10f u2 zl8101 dgnd 1 sync 2 sa0 3 sa1 4 scl 6 sda 7 salrt 8 fc 9 v0 10 v1 11 vmon 12 vtrk 14 fb+ 15 fb- 16 nc 17 isenb 18 isena 19 pwml 20 sgnd 21 vr 23 vdd 24 v25 25 xtemp 26 ddc 27 mgn 28 en 30 ss 31 pg 32 nc 5 drvctl 13 pwmh 22 nc 29 sgnd 33 c1 l1 r2 c6 ddcbus (note 21) i 2 c/smbus
fn7832 rev 1.00 page 10 of 36 july 13, 2012 zl8101 figure 3. example design using zl8101 and isl6611 phase doubler vdrv = 5v l2 l1 q2 c10 10f r3 c4 4.7f c8 0.01f c6 fb1 isena gnd gh_1 u2 isl6611airz gnd 1 lga 2 pvcc 3 gain 4 pgnd 5 lgb 6 en_ph 7 phb 8 ugb 9 bstb 10 epad 17 bsta 11 uga 12 pha 13 vcc 14 pwm 15 sync 16 sw_2a gl_2 c1 c7 drven ddc sgnd2 sgnd pg gh_2 scl r5 6.65k r1 100k en sda 4 wire inductors sw_1a fb2 c5 gl_1 vin = 4.5v-14v sgnd q1 pwmh cout1 c9 10f u1 zl8101 dgnd 1 sync 2 sa0 3 sa1 4 scl 6 sda 7 salrt 8 fc 9 v0 10 v1 11 vmon 12 vtrk 14 fb+ 15 fb- 16 nc 17 isenb 18 isena 19 pwml 20 sgnd 21 vr 23 vdd 24 v25 25 xtemp 26 ddc 27 mgn 28 en 30 ss 31 pg 32 nc 5 drvctl 13 pwmh 22 nc 29 sgnd 33 vout r2 c2 10f c3 r4 sgnd sgnd2 ddcbus (note 21) i 2 c/smbus
zl8101 fn7832 rev 1.00 page 11 of 36 july 13, 2012 typical application circuit figure 2 represents a typical application circuit for single phase applications using a zl1505 driver. other power stages like drmos devices can be substituted for the zl1505 and output fet?s. figure 3 represents a typical application circuit for 2-phase designs using a isl6611 phase doubler ic. zl8101 overview digital-dc architecture the zl8101 is an innovative mixed-signal power conversion and power management ic based on zilker labs? patented digital-dc technology that provides an integrated, high performance step-down converter for a wide variety of power supply applications. today?s embedded power systems ar e typically designed for optimal efficiency at maximum load, reducing the peak thermal stress by limiting the total thermal di ssipation inside the system. unfortunately, many of these systems are often operated at load levels far below the peak where the power system has been optimized, resulting in reduced efficiency. while this may not cause thermal stress to occur, it does cont ribute to higher electricity usage and results in higher overall system operating costs. zilker labs? efficiency-adaptive zl8101 dc-dc controller helps mitigate this scenario by enabling the power converter to automatically change their operatin g state to increase efficiency and overall performance. its unique digital pwm loop utili zes an innovative mixed signal topology to enable precise control of the power conversion process with no software required, resulting in a very flexible device that is also easy to use. an extensive set of power management functions is fully in tegrated and can be configured using simple pin connections or via the i 2 c/smbus hardware interface using standard pmbus commands. the user configuration can be saved in an on-chip non-volatile memory (nvm), allowing ultimate flexibility. once enabled, the zl8101 is immediately ready to regulate power and perform power management tasks with no programming required. the zl8101 can be configured by simply connecting its pins according to the tables provided in this document. advanced configur ation options and real-time configuration changes are available via the i 2 c/smbus interface if desired, and continuous moni toring of multiple operating parameters is possible with minimal interaction from a host controller. integrated sub-regulation circuitry enables single supply operation from any supply between 4.5v and 14v with no secondary bias supplies needed. zilker labs provides a comprehensive set of application notes to assist with power supply design and simulation. an evaluation board is also available to help th e user become familiar with the device. this board can be evaluated as a stand-alone platform using pin configuration settings. additionally, a windows?-based gui is provided to enable full configuration and monitoring capability via the i 2 c/smbus interface using an available computer and the included usb cable. please refer to www.intersil.com for access to the most up-to-date documentation or call your local intersil sales office to order an evaluation kit. figure 4. zl8101 block diagram vtrk vin pwml pwmh communication vout vdd vr isena ddc sa(0,1) scl sync isenb adc sda power management nvm salrt mosfet pre drivers ldo d-pwm sync gen digital compensator mux voltage sensor vsen+ vsen- temp sensor pg xtemp pll en ss mgn drvctl adc nlr vdd v(0,1) fc vmon adc refcn driver mosfets dac - +
zl8101 fn7832 rev 1.00 page 12 of 36 july 13, 2012 power conversion overview the zl8101 operates as a voltage-mode, synchronous buck converter with a selectable constant frequency pulse width modulator (pwm) control scheme that uses an external driver, mosfets, capacitors, and an inductor to perform power conversion. figure 5 illustrates the basic synchronous buck converter topology showing the primary power train components. this converter is also called a step-down converter, as the output voltage must always be lo wer than the input voltage. dual output pwm the zl8101 provides a dual pwm signal for use with the zl1505 driver and tri-state capable outputs for compatibility with single input drivers and drmos devices. when using the zl8101/zl1505 driver combination, higher efficiency can be obtained by enabling the zilker labs adaptive dead time algorithm. the zl1505 is a driver with two pwm inputs. using two pwm signals (pwmh and pwml) offers more options during fault event and pre-bias conditions. the zl8101 has several features to improve the power conversion efficiency. a non-linear response (nlr) loop improves th e response time and reduces the output deviation as a result of a load transient. the zl8101 monitors the power converter? s operating conditions and continuously adjusts the turn-o n and turn-off timing of the high-side and low-side mosfets to optimize the overall efficiency of the power supply. adaptive performance optimization algorithms such as dead-time control, diode emulation, and adaptive frequency are available to provide greater efficiency improvement. the zl8101 can also be used with single-ended mosfet drivers and drmos devices that require the pwmh output to tri-state when disabled. the trade-offs for using this mode may include reduced efficiency and degraded pre-bias protection depending on the minimum pulse width requirement of the single input driver. tri-state pwm outputs anytime the zl8101 has power applied and pmbus or hw enable is de-asserted, the pwmh and pwml cmos outputs are tri-stated. the pwm outputs switch between 0 and the voltage on the vr pin (typically 5v). the zl8101 pwm outputs are compatible with drivers who?s inputs are pulled between 2.5v and 5.5v. the tri-state function is always active, so no controls are provided. the zl1505 driver contains integrated pull-down resistors that deactivate the tri-state function. driver enable control (drvctl) the zl8101 includes an output pi n that can be used to control the enable pin of single input drivers and drmos devices. the drvctl pin is asserted high plus a small delay time (td ed ) when hw enable or pmbus enable is asserted. the drvctl pin is de-asserted at the end of the fall time plus a delay (td off ). see figure 6 for timing information. power management overview the zl8101 incorporates a wide range of configurable power management options that are simple to implement with no external components. the zl8101 includes circuit protection features that continuously safe guard the device and load from damage due to unexpected system faults. the zl8101 can continuously monitor input volt age, output voltage/current, internal temperature, and the temperature of an external thermal diode. a power-good output signal is also included to enable power-on reset functional ity for an external processor. all power management functions ca n be configured using either pin configuration techniques (s ee figure 7) or via the i 2 c/smbus interface. monitoring parameters can also be pre-configured to provide alerts for specific conditions. see application note an2033 for more details on smbus monitoring. multi-mode pins in order to simplify circuit design, the zl8101 incorporates patented multi-mode pins that allow the user to easily configure many aspects of the device with no programming. most power management features can be co nfigured using these pins. the multi-mode pins can respond to fo ur different connections as shown in table 1. these pins are sampled when power is applied or by issuing a pmbus restore command (see application note an2033 ). pin-strap settings this is the simplest implementation method, as no external components are required. using th is method, each pin can take on one of three possible states: low, open, or high. these pins can be connected to the v25 pin for logic high settings as this pin provides a regulated voltage higher than 2v. using a single pin, one of three settings can be selected. using two pins, one of nine settings ca n be selected. figure 5. synchronous buck converter driver pwml gh pwmh gl zl8101 gh gl cout vout vin figure 6. drvctl and tri-state behavior drvctl en pwmh vout pwml 3s off_delay t fall t on_delay t rise t off_delay tri-state tri-state tri-state td ed td off
zl8101 fn7832 rev 1.00 page 13 of 36 july 13, 2012 resistor settings this method allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multi-mode pin and sgnd. standard 1% resistor values are used, and only every fourth e96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. up to 31 unique selections are available using a single resistor. i 2 c/smbus method almost all zl8101 functions can be configured via the i 2 c/smbus interface using standard pmbus commands. any value that has been configured using the pin-stra p or resistor setting methods can also be re-configured and/or verified via the i 2 c/smbus. see application note an2033 for more details. the smbus device address and vout_max are the only parameters that must be set by external pins. all other device parameters can be set via the i 2 c/smbus. the device address is set using the sa0 and sa1 pins. vout_max is set to 10% greater than the voltage set by the v0 and v1 pins. power conversion functional description internal bias regulators and input supply connections the zl8101 employs two internal low dropout (ldo) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. the internal bias regulators are as follows: ? vr: the vr ldo provides a regulated 5v bias supply for the mosfet pre-driver circuits. it is powered from the vdd pin. a 4.7 to 10f filter capacitor is required at the vr pin. to ensure regulator stability, capacitors outside of this range must not be used. ? v25: the v25 ldo provides a regulated 2.5v bias supply for the main controller circuitry. it is powered from an internal 5v node. a 4.7 to 10f filter capacitor is required at the v25 pin. to ensure regulator stability capacitors outside of this range must not be used. when the input supply (vdd) is high er than 5.5v, the vr pin should not be connected to any other pins. it should only have a filter capacitor attached as shown in figure 8. due to the dropout voltage associated with the vr bias re gulator, the vdd pin must be connected to the vr pin for design s operating from a supply below 5.5v. figure 8 illustrates the requ ired connections for both cases. note : the internal bias regulators are not designed to be outputs for powering other circuitry. do not attach external loads to any of these pins. the multi-mode pins may be connected to the v25 pin for logic high settings. output voltag e selection standard mode the output voltage may be set to any voltage between 0.6v and 3.6v provided that the input volt age is higher th an the desired output voltage by an amount su fficient to prevent the device from exceeding its maximum duty cycle specification. using the pin-strap method, v out can be set to any of nine standard voltages as shown in table 2. the resistor setting method can be used to set the output voltage to levels not available in table 2. resistors r0 and r1 are selected to produce a specific voltage between 0.6v and 3.6v in 10mv steps. resistor r1 provides a coarse setting and resistor r0 provides a fine adjustment, thus eliminating the additional errors associated with using two 1% resistors (this typically adds 1.4% error). to set v out using resistors, follow the steps below to calculate an index value and then use table 3 to select the resistor that corresponds to the calculated index value as follows: 1. calculate index1: index1 = 4 x v out (v out in 10mv steps) 2. round the result down to the nearest whole number. table 1. multi-mode pin configuration pin tied to value low (logic low) <0.8vdc open (n/c) no connection high (logic high) >2.0vdc resistor to sgnd set by resistor value figure 7. pin-strap and resistor setting examples zl multi-mode pin zl r set logic high logic low open pin-strap settings resistor settings multi-mode pin figure 8. input supply connections v in vdd vr zl8101 v in vdd vr zl8101 5.5v < v in 14v 4.5v v in 5.5v
zl8101 fn7832 rev 1.00 page 14 of 36 july 13, 2012 3. select the value of r1 from table 3 using the index1 rounded value from step 2. 4. calculate index0: index0 = 100 x v out ? (25 x index1) 5. select the value of r0 from table 3 using the index0 value from step 4. example from figure 9: for v out = 1.33v, index1 = 4 x 1.33v = 5.32; from table 3, r1 = 16.2k index0 = (100 x 1.33v) ? (25 x 5) = 8; from table 3, r0 = 21.5k the output voltage can be determined from the r0 (index0) and r1 (index1) values using equation 1: the output voltage may also be set to any value between 0.6v and 3.6v using the i 2 c interface. see application note an2033 for details. single resistor output voltage setting mode some applications desire the output voltage to be set using a single resistor. this can be acco mplished using a resistor on the v1 pin while the v0 pin is tied to sgnd. table 4 lists the available output voltage settings with a si ngle resistor. see application note an2033 for more details. table 3. resistors for setting output voltage index r0 or r1 (k ) 010 111 2 12.1 3 13.3 4 14.7 516.2 617.8 7 19.6 821.5 9 23.7 10 26.1 11 28.7 12 31.6 13 34.8 14 38.3 15 42.2 16 46.4 17 51.1 18 56.2 19 61.9 20 68.1 21 75 22 82.5 23 90.9 24 100 100 ) 1 index 25 ( 0 index out v ? ? ? ? r v0 v out 10 low 0.60 11 low 0.65 12.1 low 0.70 13.3 low 0.75 14.7 low 0.80 16.2 low 0.85 17.8 low 0.90 19.6 low 0.95 21.5 low 1.00 23.7 low 1.05 26.1 low 1.10 28.7 low 1.15 31.6 low 1.20 34.8 low 1.25 38.3 low 1.30 42.2 low 1.40 46.4 low 1.50 51.1 low 1.60 56.2 low 1.70 61.9 low 1.80 68.1 low 1.90 75.0 low 2.00 82.5 low 2.10 90.9 low 2.20 100 low 2.30 figure 9. output voltage resistor setting example zl8101 gh gl v0 v1 dr iver vin vout r0 21.5k r1 16.2k
zl8101 fn7832 rev 1.00 page 15 of 36 july 13, 2012 start-up procedure the zl8101 follows a specific internal start-up procedure after power is applied to the vdd pin. table 5 describes the start-up sequence. if the device is to be synchronized to an external clock source, the clock frequency must be stable pr ior to asserting the en pin. the device requires approximately 5ms to 10ms to check for specific values stored in its internal memory. if the user has stored values in memory, those values will be loaded. the device will then check the status of all multi-mo de pins and load the values associated with the pin settings. once this process is completed, the device is ready to accept commands via the i 2 c/smbus interface and the device is ready to be enabled. once enabled, the device requires approximately 2ms before its output voltage may be allowed to start its ramp-up process. if a soft-start delay period less than 2ms has been configured (using pmbu s commands), the device will default to a 2ms delay period (wit h an accuracy of approximately 0.25ms). if a delay period greater than 2ms is configured, the device will wait for the configured delay period prior to starting to ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft-start ramp time that has been set using the ss pin. soft-start delay and ramp times in some applications, it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current management strategy or to precisely control how fast a load ic is turned on. the zl8101 gives the system designer several options for precisely and independently controlling both th e delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay period is set using the ss pin. the soft-start ramp timer enables a precisely controlled ramp to the nominal v out value that begins once the delay period has expired. the ramp-up is guarante ed monotonic and its slope may be precisely set using the ss pin. the soft-start delay and ramp times can be set to standard values according to table 6. 110 low 2.50 121 low 3.00 133 low 3.30 147 low 4.00 162 low 5.00 178 low 5.50 table 4. (continued) r v1 (k ? r v0 v out table 5. zl8101 start-up sequence step # step name description time duration 1 power applied input voltage is applied to the zl8101?s vdd pin depends on input supply ramp time 2 internal memory check the device will check for va lues stored in its internal memory. this step is also performed after a restore command. approx 5ms to 10ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi-mode pin check the device loads values configured by the multi-mode pins. 4 device ready the device is ready to accept an enable signal. - 5 pre-ramp delay the device requires approximately 2ms following an enable signal and prior to ramping its output. additional pre-ramp delay may be configured using the delay pins. approximately 2ms
zl8101 fn7832 rev 1.00 page 16 of 36 july 13, 2012 . note that when auto compensation is enabled, the minimum ton_delay is 5ms. the value of this resistor is measured upon start-up or restore and will not change if the resistor is varied after power has been applied to the zl8101. see figure 10 for typical connections using resistors. if the desired soft-start delay and ramp times are not one of the values listed in table 6, the times can be set to a custom value via the i 2 c/smbus interface. when the ss delay time is set to 0ms, the device will begin its ramp after the internal circuitry has initialized (~2ms). the soft-start ramp period may be set to values less than 2ms, however it is generally recommended to set the soft-start ramp to a value greater than 500s to pr event inadvertent fault conditions due to excessive inrush current. power-good the zl8101 provides a power-good (pg) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. by de fault, the pg pin will assert if the output is within -10%/+15% of the target voltage. these limits and the polarity of th e pin may be changed via the i 2 c/smbus interface. see application note an2033 for details. a pg delay period is defined as the time from when all conditions within the zl8101 for asserting pg are met, to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. by default, the zl8101 pg delay is set equal to the soft-start ramp time setting. therefore, if the soft-start ramp time is set to 10ms, the pg delay will be set to 10ms. the pg delay may be set independently of the soft-start ramp using the i 2 c/smbus as described in application note an2033. switching frequency and pll the zl8101 incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pl l can be driven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source for other zilker labs devices. the sync pin is a unique pin that can perform multiple functions depending on how it is configured. table 6. soft-start ramp settings r ss (k ) ss delay (ms) ss ramp (ms) uvlo (v) low 2 2 4.5 open 5 5 high 10 10 10 2 2 4.5 11 5 12.1 10 13.3 5 2 14.7 5 16.2 10 17.8 20 19.6 10 2 21.5 5 23.7 10 26.1 20 28.7 20 2 31.6 5 34.8 10 38.3 20 42.2 2 2 10.8 46.4 5 51.1 10 56.2 20 61.9 5 2 68.1 5 75 10 82.5 20 90.9 10 2 100 5 110 10 121 20 133 20 2 147 5 162 10 178 20 figure 10. ss pin resistor connections zl8101 ss r ss
zl8101 fn7832 rev 1.00 page 17 of 36 july 13, 2012 configuration a: sync output when the sync pin is configured as an output, the device will run from its internal oscillator and will drive the resulting internal oscillator signal (preset to 400kh z) onto the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. this mode is only available using the i 2 c/smbus as described in application note an2033. configuration b: sync input when the sync pin is configured as an input, the device will automatically check for a clock sign al on the sync pin each time en is asserted. the zl8101?s oscillator will then synchronize with the rising edge of the external clock. the internal clock must be configured to the nearest available frequency to the external clock, to minimize output pertur bations if the external clock is lost. the incoming clock signal must be in the range of 200khz to 1.4mhz and must be stable when the enable pin is asserted. the clock signal must also exhi bit the necessary performance requirements (see the ?electrica l specifications? table beginning on page 6). in the event of a loss of the external clock signal, the output voltage may show transient over/undershoot. if this happens, the zl8101 wi ll automatically switch to its internal oscillator and switch at a frequency close to the previous incoming frequency. this mode is only available using the i 2 c/smbus as described in application note an2033 . sync auto detect when the sync pin is configured in auto detect mode, the device will automatically check for a clock signal on the sync pin after enable is asserted. if a clock signal is present, the zl8101?s oscillator will then synchronize the rising edge of the external clock. if no incoming clock signal is present, the zl8101 will configure the switching frequency according to the state of the sync pin as listed in table 7. in this mode, the zl8101 will only read the sync pin connection during the start-up sequence. changes to sync pin connections will not affect f sw until the power (vdd) is cycled off and on. if the user desires to configure other frequencies not listed in table 7, the switching frequency can also be set to any value between 200khz and 1.33mhz using the i 2 c/smbus interface. the available frequencies below 1.4mhz are defined by f sw = 8mhz/n, where 6 ? n ?? 40. see application note an2033 for details. if a value other than f sw = 8mhz/n is entered using a pmbus command, the internal circuitry will select the switching frequency value using n as a whole number to achieve a value close to the entered value. for example, if 810khz is entered, the device will select 800khz (n = 10). when multiple zilker labs devices are used together, connecting the sync pins together will force all devices to synchronize with each other. one of the devices must be configured as a sync source and the remaining devices must be configured as a sync input. the i 2 c/smbus must be used to configure the sync pin. figure 11. sync pin configurations r26 sync zl8101 200khz to 1.33mhz sync = output sync 200khz to 1.33mhz sync = input or auto detect zl8101 sync zl8101 logic low logic high open sync zl8101 ) f sw (khz) 10 200 11 222 12.1 242 13.3 267 14.7 296 16.2 320 17.8 364 19.6 400 21.5 421 23.7 471 26.1 533 28.7 571 31.6 615 34.8 727 38.3 800 46.4 889 51.1 1000 56.2 1143 68.1 1333
zl8101 fn7832 rev 1.00 page 18 of 36 july 13, 2012 note : the switching frequency read back using the appropriate pmbus command will differ slightly from the selected values in table 8. the difference is due to hardware quantization. power train component selection the zl8101 is a synchronous buck converter that uses external driver, mosfets, inductor and capacitors to perform the power conversion process. the proper selection of the external components is critical for optimized performance. to select the appropriate external components for the desired performance goals, the power supply requirements listed in table 9 must be known. design goal trade-offs the design of the buck power stage requires several compromises among size, efficiency , and cost. the inductor core loss increases with frequency, so there is a trade-off between a small output filter made possible by a higher switching frequency and getting better power supply efficiency. size can be decreased by increasing the switching frequency at the expense of efficiency. cost can be minimized by using through-hole inductors and capacitors; however these components are physically large. to start the design, select a switching frequency based on table 10. this frequency is a starting point and may be adjusted as the design progresses. driver selection the zl8101 requires an external driver, the recommended 2-input companion driver is the zl1505 with integrated 30v bootstrap schottky diode. the zl1505 has independent pwmh and pwml inputs to take advantage of the dynamic dead-time control on the zl8101. the zl8101 can be used with other driver devices, like the isl6611 phase doubler driver and several drmos type drivers. please check with intersil if you are not sure about compatibility. inductor selection the output inductor selection process must include several trade-offs. a high inductance value will result in a low ripple current (i opp ), which will reduce output capacitance and produce a low output ripple voltage, but may also compromise output transient load performance. therefore, a balance must be struck between output ripple and optimal load transient performance. a good starting point is to select the output inductor ripple equal to the expected load transient step magnitude (i ostep ): now the output inductance can be calculated using equation 3, where v inm is the maximum input voltage: the average inductor current is equal to the maximum output current. the peak inductor current (i lpk ) is calculated using equation 4 where i out is the maximum output current: select an inductor rated for the average dc current with a peak current rating above the peak cu rrent computed in equation 4. in overcurrent or short-circuit conditions, the inductor may have currents greater than 2x the normal maximum rated output current. it is desirable to use an inductor that still provides some inductance to protect the load and the mosfets from damaging currents in this situation. once an inductor is selected, the dcr and core losses in the inductor are calculated. use the dcr specified in the inductor manufacturer?s datasheet. i lrms is given by equation 6: where i out is the maximum output current. next, calculate the core loss of the selected inductor. since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor datasheet. add the core loss and the esr loss and compare the total loss to th e maximum power dissipation recommendation in the inductor datasheet. table 9. power supply requirements parameter range example value input voltage (v in ) 4.5v to 14.0v 12v output voltage (v out ) 0.6v to 3.6v 1.2v output current (i out ) 0a to ~25a 20a output voltage ripple (v orip ) < 3% of v out 1% of v out output load step (i ostep )< i o 50% of i o output load step rate - 10a/s output deviation due to load step - 50mv maximum pcb temp. +120c +85c desired efficiency - 85% other considerations various optimize for small size table 10. circuit design considerations frequency range efficiency circuit size 200khz to 400khz highest larger 400khz to 800khz moderate smaller 800khz to 1.4mhz lower smallest ostep opp i i ? opp sw inm out out out i f v v v l ? ? ? ? ? ? ? ? ? ? ? ? 1 2 opp out lpk i i i ? ? 2 lrms ldcr i dcr p ? ? ?? 12 2 2 opp out lrms i i i ? ?
zl8101 fn7832 rev 1.00 page 19 of 36 july 13, 2012 output capacitor selection several trade-offs must also be considered when selecting an output capacitor. low esr values are needed to have a small output deviation during transient load steps (v osag ) and low output voltage ripple (v orip ). however, capacitors with low esr, such as semi-stable (x5r and x7r) dielectric ceramic capacitors, also have relatively low capacitance values. many designs can use a combination of high capacitance devices and low esr devices in parallel. for high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. likewise, in high transient load steps, a relatively large amount of capacitance is needed to minimize the output voltage deviation while the inductor current ramps up or down to the new steady state output current value. as a starting point, apportion one-half of the output ripple voltage to the capacitor esr and the other half to capacitance, as shown in equations 7 and 8: use these values to make an init ial capacitor selection, using a single capacitor or several capacitors in parallel. after a capacitor has been select ed, the resulting output voltage ripple can be calculated using equation 9: because each part of this equation was made to be less than or equal to half of the allowed output ripple voltage, the v orip should be less than the desired maximum output ripple. input capacitor it is highly recommended that dedicated input capacitors be used in any point-of-load design, even when the supply is powered from a heavily filtered 5v or 12v ?bulk? supply from an off-line power supply. this is because of the high rms ripple current that is drawn by the buck converter topology. this ripple (i cinrms ) can be determined from equation 10: without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. the input capacitors should be rated at 1.2x the ripple current calculated above to avoid overheating of the capacitors due to the high ripple current, which can cause premat ure failure. ceramic capacitors with x7r or x5r dielectric with low esr and 1.1x the maximum expected input voltage are recommended. ql selection the bottom mosfet should be selected primarily based on the device?s r ds(on) and secondarily based on its gate charge. to choose ql, use equation 11 and allow 2% to 5% of the output power to be dissipated in the r ds(on) of ql (lower output voltages and higher step-down ratios will be closer to 5%): calculate the rms current in ql as follows: calculate the desired maximum r ds(on) as follows: note that the r ds(on) given in the manufacturer?s datasheet is measured at +25c. the actual r ds(on) in the end-use application will be much higher. for example, a vishay si7114 mosfet with a junction temperature of +125c has an r ds(on) that is 1.4 times higher than the value at +25c. select a candidate mosfet, and calculate the required gate drive current as follows: keep in mind that the total allowed gate drive current for both qh and ql is 80ma. mosfets with lower r ds(on) tend to have higher gate charge requirements, which increases th e current and resulting power required to turn them on and of f. since the mosfet gate drive circuits are integrated in the zl150 5, this power is dissipated in the zl1505 according to equation 15: qh selection in addition to the r ds(on) loss and gate charge loss, qh also has switching loss. the procedure to select qh is similar to the procedure for ql. first, assign 2% to 5% of the output power to be dissipated in the r ds(on) of qh using the equation 11 for ql. as was done with ql, calculate the rms current as follows: calculate a starting r ds(on) as follows, in this example using 5%: select a mosfet and calculate the resulting gate drive current. verify that the combined gate drive current from ql and qh does not exceed 80ma. 2 8 orip sw opp out v f i c ? ? ? opp orip i v esr ? ? 2 out sw opp opp orip c f i esr i v ? ? ? ? ? 8 ) 1 ( d d i i out cinrms ? ? ? ? out out ql i v p ? ? ? 05 . 0 d i i lrms botrms ? ? ? 1 ?? 2 ) ( botrms ql on ds i p r ? g sw g q f i ? ? inm g sw ql v q f p ? ? ? d i i lrms toprms ? ? out out qh i v p ? ? ? 05 . 0 ?? 2 ) ( toprms qh on ds i p r ?
zl8101 fn7832 rev 1.00 page 20 of 36 july 13, 2012 next, calculate the switching time using equation 19: where q g is the gate charge of the selected qh and i gdr is the peak gate drive current available from the zl1505. although the zl1505 has a typical gate drive current of 3.2a, use the minimum guaranteed current of 2a for a conservative design. using the calculated switching time, calculate the switching power loss in qh using equation 20: the total power dissipated by qh is given by equation 21: mosfet thermal check once the power dissipations for qh and ql have been calculated, the mosfet?s junction temperature can be estimated. using the junction-to-case thermal resistance (r th ) given in the mosfet manufacturer?s datasheet and the expected maximum printed circuit board temperature, calcul ate the junction temperature as shown in equation 22: current sensing components once the current sense method has been selected (refer to ?current limit threshold selection? on page 22), the components are selected as follows. when using the inductor dcr sensing method, the user must also select an r/c network co mprised of r1 and cl (see figure 12). for the voltage across c l to reflect the voltage across the dcr of the inductor, the time constant of the inductor must match the time constant of the rc network. that is: for l, use the average of the nominal value and the minimum value. include the effects of tolerance, dc bias and switching frequency on the inductance when determining the minimum value of l. use the typical value for dcr. the value of r 1 should be as small as feasible and no greater than 5k for best signal-to-noise ratio. the designer should make sure the resistor package size is appropriate for the power dissipated and include this loss in efficiency calculations. in calculating the minimum value of r 1 , the average voltage across c l (which is the average i out dcr product) is small and can be neglected. therefore, the minimum value of r 1 may be approximated by equation 24: where p r1pkg - max is the maximum power dissipation specification for the resistor package and p is the derating factor for the same parameter (e.g.: p r1pkg - max = 0.0625w for 0603 package, p = 50% @ +85c). once r 1 - min has been calculated, solve for the maximum value of c l from equation 25: and choose the next-lowest readily available value (e.g., for c l - max = 1.86f, c l = 1.5f is a good choice). then substitute the chosen value into the same equation and re-calculate the value of r 1 . choose the 1% resistor standard value closest to this re-calculated value of r 1 . the error due to the mismatch of the two time constants is: current limit threshold selection it is recommended that the user include a current limiting mechanism in their design to protect the power supply from damage and prevent excessive current from being drawn from the input supply in the event that the output is shorted to ground or an overload condition is imposed on the output. current limiting is accomplished by sensing the current through the circuit during a portion of the duty cycle. output current sensing can be accomplished by measuring the voltage across a series resistiv e sensing element according to equation 27: where: i lim is the desired maximum current that should flow in the circuit r sense is the resistance of the sensing element v lim is the voltage across the sensing element at the point the circuit should start limiting the output current. the zl8101 supports ?lossless? current sensing, by measuring the voltage across a resistive element that is already present in the circuit. this eliminates addi tional efficiency losses incurred by devices that must use an addi tional series resistance in the circuit. to set the current limit threshold, the user must first select a current sensing method. the zl8101 incorporates inductor dc gdr g sw i q t ? sw out sw inm swtop f i t v p ? ? ? ? swtop qh qhtot p p p ? ? ?? th q pcb j r p t t ? ? ? max figure 12. dcr current sensing driver isenb isena pwmh pwml vi n cl l1 r1 cout vout dcr l c r l dcr l rc ? ? ? 1 / ? ? ???? p pkg r out out in p v d v v d r ? ? ? ? ? ? ? ? ? ? max 1 2 2 max min 1 1 dcr r l c l ? ? ? ? min 1 max % 100 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? avg l l dcr c r ? ? sense lim lim r i v ? ?
zl8101 fn7832 rev 1.00 page 21 of 36 july 13, 2012 resistance (dcr) sensing; fi gure 12 shows a simplified schematic for dcr method. r ds(on) method is not supported. advanced ilim pinstrapping options are not available for the zl8101. however, all current limit and fault response options are available when using i 2 c/smbus interface and configuration file. the blanking time represents the time when no current measurement is taken. this is to avoid taking a reading just after a coincident switching edge (less accurate due to potential ringing). blanking time is a configurable parameter. zl8101 provides an adjustable maximum full scale sensing range. the available ranges are 25mv, 35mv and 50mv using the i 2 c/smbus interface or a configuration file. table 11 lists the factory default value for the current limit function. the user must select the voltag e threshold (vlim), the desired current limit threshold, and the resistance of the sensing element. the current limit threshold must be set to a custom value via the i 2 c/smbus interface. please refer to application note an2033 for further details. loop compensation the zl8101 has an auto compensation feature that measures the characteristics of the power train and calculates the proper tap coefficients. auto compensati on is configured using the fc pin as shown in table 12. table 11. factory default ilim configuration current limiting configuration number of violations allowed current limit threshold v lim (mv) maximum current sensing range (mv) output-referenced, down-slope sensing (inductor dcr sensing) blanking time: 480ns 750 50 table 12. pin #9 (fc) auto compensation mode r fc (k )store values single/ repeat pg assert auto comp gain low auto comp disabled open not stored single after auto comp 100% high store in flash single after auto comp 10 not stored single after auto comp 100% 11 store in flash 12.1 not stored repeat 1s 13.3 store in flash 14.7 not stored single after pg delay 16.2 store in flash 17.8 not stored repeat 1s 19.6 store in flash open not stored single after auto comp high/ 21.5 store in flash 23.7 not stored repeat 1min 26.1 store in flash 28.7 not stored single after pg delay 31.6 store in flash 34.8 not stored repeat 1min 38.3 store in flash 42.2 not stored single after auto comp 50% 46.4 store in flash 51.1 not stored repeat 1s 56.2 store in flash 61.9 not stored single after pg delay 68.1 store in flash 75 not stored repeat 1s 82.5 store in flash 90.9 not stored single after auto comp 100 store in flash 110 not stored repeat 1min 121 store in flash 133 not stored single after pg delay 147 store in flash 162 not stored repeat 1min 178 store in flash table 12. pin #9 (fc) auto compensation mode (continued) r fc (k )store values single/ repeat pg assert auto comp gain
zl8101 fn7832 rev 1.00 page 22 of 36 july 13, 2012 when auto compensation is enabled, the routine can be set to execute one time after ramp or periodically while regulating. note that the auto compensation feature requires a minimum ton_delay as described in "sof t-start delay and ramp times" on page 16. if the device is configured to store auto comp values, the calculated compensation values will be saved in the auto comp store and may be read back through the pid_taps command. if repeat mode is enabled, the first auto comp results after the first ramp will be stored; the values calculated periodically are not stored in the auto comp store. when compensation values are saved in the auto comp store, the device will use those compensation values on subsequent ramps. in repeat mode, the latest auto comp results will always be used during operation. stored auto comp results can only be cleared by disabling auto comp store, which is not permitted while the output is enabled. however, sending the autocomp_control command while enabled in store mode will cause the next results to be stored, overwriting previously stored values. if auto compensation is disabled, the device will use the compensation parameters that are stored in the default_store or user_store. if the pg assert parameter is set to "use pg delay," pg will be asserted according to the power_good_delay command. when auto comp is enabled, the user must not program a power-good delay that will expire before the ramp is finished. if pg assert is set to "after auto comp," pg will be asserted immediately after the first auto comp cycle completes (power_good_delay will be ignored). the auto comp gain control scales the auto comp results to allow a trade-off between transient response and steady-state duty cycle jitter. a setting of 100% will provide the fastest tr ansient response while a setting of 10% will produce the lowest jitt er. note that if auto comp is enabled, for best results vin must be stable before auto comp begins, as shown in equation 28. the auto compensation function can also be configur ed via the auto_comp_config command and controlled using the auto_comp_control command over the i 2 c/smbus interface. please refer to application note an2033 for further details. non-linear response (nlr) settings the zl8101 incorporates a non-lin ear response (nlr) loop that decreases the response time and the output voltage deviation in the event of a sudden output load current step. the nlr loop incorporates a secondary error signal processing path that bypasses the primary error loop when the output begins to transition outside of the standard regulation limits. this scheme results in a higher equivalent loop bandwidth than what is possible using a traditional linear loop. when a load current step function imposed on the output causes the output voltage to drop below the lower regulation limit, the nlr circuitry will force a positive correction signal that will turn on the upper mosfet and quickly force the output to increase. conversely, a negative load step (i.e., removing a large load current) will cause the nlr circuitry to force a negative correction signal that will turn on the lower mosfet and quickly force the output to decrease. the zl8101 has been pre-configured with appropriate nlr settings that correspond to the loop compensation settings in table 13. efficiency optimize d driver dead-time control the zl8101 utilizes a closed loop algorithm to optimize the dead-time applied between the gate drive signals for the top and bottom fets. in a synchronous buck converter, the mosfet drive circuitry must be designed such that the top and bottom mosfets are never in the conduc ting state at the same time. potentially damaging currents flow in the circuit if both top and bottom mosfets are simultaneously on for periods of time exceeding a few nanoseconds. conversely, long periods of time in which both mosfets are off reduce overall circuit efficiency by allowing current to flow in their parasitic body diodes. it is therefore advantageous to minimize this dead-time to provide optimum circuit efficiency. in the first order model of a buck converter, the duty cycle is determined by equation 29: however, non-idealities exist that cause the real duty cycle to extend beyond the ideal. dead-tim e is one of those non-idealities that can be manipulated to improve efficiency. the zl8101 has an internal algorithm that constantly adjusts dead-time non-overlap to minimize duty cycle, thus maximizing efficiency. this circuit will null out dead-time differences due to component variation, temperature, and loading effects. this algorithm is independent of application circuit parameters such as mosfet type, gate driver delays, rise and fall times and circuit layout. in addition, it does not require drive or mosfet voltage or current waveform measurements. ? vin vin nom --------------------- in% ?? 100% 1 256 vout ? vin nom ----------------------------- + -------------------------------------- - ? (eq. 28) in out v v d ?
zl8101 fn7832 rev 1.00 page 23 of 36 july 13, 2012 table 13. pin-strap settings for loop compensation nlr f n range f zesr range fc pin (k ) off f sw /60 < f n < f sw /30 f zesr > f sw /10 10 f sw /10 > f zesr > f sw /30 11 f sw /30 > f zesr > f sw /60 12.1 f sw /120 < f n < f sw /60 f zesr > f sw /10 13.3 f sw /10 > f zesr > f sw /30 14.7 f sw /30 > f zesr > f sw /60 16.2 f sw /240 < f n < f sw /120 f zesr > f sw /10 17.8 f sw /10 > f zesr > f sw /30 19.6 f sw /30 > f zesr > f sw /60 21.5 on f sw /60 < f n < f sw /30 f zesr > f sw /10 23.7 f sw /10 > f zesr > f sw /30 26.1 f sw /30 > f zesr > f sw /60 28.7 f sw /120 < f n < f sw /60 f zesr > f sw /10 31.6 f sw /10 > f zesr > f sw /30 34.8 f sw /30 > f zesr > f sw /60 38.3 f sw /240 < f n < f sw /120 f zesr > f sw /10 42.2 f sw /10 > f zesr > f sw /30 46.4 f sw /30 > f zesr > f sw /60 51.1
zl8101 fn7832 rev 1.00 page 24 of 36 july 13, 2012 adaptive diode emulation most power converters use synchronous rectification to optimize efficiency over a wide range of input and output conditions. however, at light loads the synchronous mosfet will typically sink current and introduce additi onal energy losses associated with higher peak inductor currents, resulting in reduced efficiency. adaptive diode emulation mode turns off the low-side fet gate drive at low load currents to prevent the inductor current from going negative, reducing th e energy losses and increasing overall efficiency. diode emulation is available to single-phase devices only. note: the overall bandwidth of the device may be reduced when in diode emulation mode. it is recommended that diode emulation is disabled prior to applying significant load steps. power management functional description input undervoltage lockout the input undervoltage lockout (uvlo) prevents the zl8101 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 4.5v and 10.8v using the ss pin. the simplest implementation is to connect the ss pin as shown in table 6. the uvlo voltage can also be set to any value between 2.85v and 16v via the i 2 c/smbus interface. once an input undervoltage faul t condition occurs, the device can respond in a number of ways as follows: 1. continue operating without interruption. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device will remain in shutdown until instructed to restart. 3. initiate an immediate shutdo wn until the fault has been cleared. the user can select a specific number of retry attempts. the default response from a uvlo fault is an immediate shutdown of the device. the devi ce will continuously check for the presence of the fault condition. if the fault condition is no longer present, the zl8101 will be re-enabled. please refer to application note an2033 for details on how to configure the uvlo threshold or to select specific uvlo fault response options via the i 2 c/smbus interface. output overvoltage protection the zl8101 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the vsen pin) to a threshold set to 15% higher than the target output voltage (t he default setting). if the vsen voltage exceeds this threshold, the pg pin will de-assert and the device can then respond in a number of ways as follows: 1. initiate an immediate shutdo wn until the fault has been cleared. the user can select a specific number of retry attempts. 2. turn off the high-side mosfet and turn on the low-side mosfet. the low-side mosfet remains on until the device attempts a restart. the default response from an over voltage fault is to immediately shut down. the device will contin uously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re-enabled. for continuous overvoltage protec tion when operating from an external clock, the only allowed response is an immediate shutdown. refer to an2033 for details on how to select specific overvoltage fault response options. output pre-bias protection an output pre-bias condition exists when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. after enable is asserted the output voltage is sampled and the initial pulse width is set to match the existing pre-bias voltage and both drivers become active. the output voltage is then ramped to the target output voltage value at a rate equal to the configured t rise . when using single input drivers or drmos devices the pre-bias is accommodated with the tri-state pwmh and drvctl outputs. when drvctl is deasserted the control and sync fet gates are active low. when drvctl is asserted pwmh becomes tri-state and both fet gates remain active low. after the configured t on_delay pwmh is adjusted to match the pre-bias voltage and vout will begin ramping from the pre-bias value. see figure 13. when powering down into a pre-bias vout is driven to 0v at a rate equal to the configured tf all. after the tri-state delay (3s_delay) pwmh becomes tri-stated and vout will transition towards the pre-bias voltage. after the tri-state delay off period (td off ) drvctl de-asserts coincidently with pwmh going active low. both the control and sync fet will be active low and vout will ramp towards the pre-bias voltage. see figure 14. minimum duty cycle the zl8101 is capable of producing output pulses as small as 5ns, however external drivers are not capable of pulses smaller then their minimum processing requirement. the minimum figure 13. turn-on into pre-bias drvctl en vout t on_delay prebias pwmh t rise td ed
zl8101 fn7832 rev 1.00 page 25 of 36 july 13, 2012 required pulse width is often specified in the product data sheet. if the external driver is presented with pulse(s) below the minimum requirement the control pulse will not be processed and the gate- high output pulse will not be present. the driver will still deliver a complementary gate-low pulse. if a pre-bias is present the output will discharge towards zero until the pwm input is wide enough to meet the minimum required by the driver, this affect is shown in figure 15. to ensure that pwm pulses below the required minimum are not produced enable the minimum duty cycle feature located within the user_config field and select the option that is slightly above the minimum value required by the driver. the actual minimum duty cycle time is given by eq 30. n = minimum duty cycle count tsw = period of switching frequency minduty = minimum duty cycle time the minimum duty cycle parameter is also required to be set when configuring current sharing, enabling minimum a minimum duty cycle ensures that each controller produces a known initial pulse which helps balance inter-phase currents during ramps. configure the minimum duty cycle to be slightly above the value specified in the driver data sheet. the minimum duty cycle parameter is part of the user_config field and is comprised of the last 3 msb?s. the range of configurable values is shown below in table 14. output overcurrent protection the zl8101 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. once the current lim it threshold has been selected (see ?current limit threshold se lection? on page 20), the user may determine the desired course of action in response to the fault condition. the following overcurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. the default response from an ov ercurrent fault is an immediate shutdown of the device. the device will continuously check for the presence of the fault condition, and if the fault condition no longer exists the device will be re-enabled. refer to an2033 for details on how to select specific overcurrent fault response options. thermal overload protection the zl8101 includes an on-chip thermal sensor that continuously measures the internal temperature of the die and shuts down the device when the temperature exceeds the preset limit. the default temperature limit is set to +125c in the factory, but the user may set the limit to a different value if desired. see application note an2033 for details. note that setting a higher thermal limit via the i 2 c/smbus interface may result in permanent damage to the device. once the device has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: figure 14. turn_off with pre_bias drvctl en vout 3s_delay t off_delay prebias tri-state pwmh t fall td off figure 15. initial pwm below minimum requirement vout pwmh g_hi missing gate pulses g_lo prebias minduty n tsw 256 ----------- ? = (eq. 30) table 14. user_config min duty hex values minimum duty cycle minimum duty count user_config disabled 0x00xx 2 0x40xx 4 0x80xx 6 0xc0xx 8 0x20xx 10 0x60xx 12 0xa0xx 14 0xe0xx
zl8101 fn7832 rev 1.00 page 26 of 36 july 13, 2012 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the device to restart, the device will wait the preset delay period (if configured to do so) and will then check the device temperature. if the temperature has dropped below a threshold that is approximately +15c lower than the selected temperature fault limit, the device will attempt to re-start. if the temperature still exceeds the fault limit the device will wait the preset delay period and retry again. the default response from a temperature fault is an immediate shutdown of the device. the devi ce will continuously check for the fault condition, and once th e fault has cleared the zl8101 will be re-enabled. voltage tracking high performance systems place stringent demands on the order in which the power supply voltages are turned on. this is particularly true when powering fpgas, asics, and other advanced processor devices that require multiple supply voltages to power a single die. in most ca ses, the i/o interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the i/o supply voltage according to the manufacturers' specifications. voltage tracking protects these sensitive ics by limiting the differential voltage among multiple power supplies during the power-up and power-down sequence. the zl8101 integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the vtrk pin with no extra components required. the vtrk pin is an analog input that, when tracking mode is enabled, configures the voltage applied to the vtrk pin to act as a reference for the device?s output regulation. voltage tracking can be configured by pin-strapping or pmbus, an example of each configuration is shown in figures 16 and 17. the zl8101 offers two modes of tracking: coincident and ratiometric. figure 18 and figure 19 illustrate the output voltage for the two tracking modes. 1. coincident . this mode configures the zl8101 to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. two options are available for this mode; - track at 100% vout limited. member rail tracks the reference rail and stops wh en the member reaches its configured target voltage. figure 18 a. - track at 100% vtrk limited. member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin. figure 18 b. 2. ratiometric . this mode configures the zl8101 to ramp its output voltage as a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor may be used to configure a different tracking ratio. - track at 50% vout limited. member rail tracks the reference rail and stops when the me mber reaches 50% of the reference?s target voltage, table 15. - track at 50% vtrk limited. member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin until the member rail reaches 50% of the reference rail voltage, or if the member is configured to less than 50% of the reference the member will achieve its configured target, table 15. figure 16. pinstrap tracking ss reference zl8101 en sw ss member zl8101 en sw vtrk r1 r2 cout_r1 l1 cout_m1 l2 hw_en vout_r vout_mem figure 17. pmbus tracking reference zl8101 sda sw scl member zl8101 sda sw scl vtrk scl sda l1 cout_r vout_r cout_m l2 vout_mem figure 18. coincident tracking en 0 0 en ~ ~ a. b. track @ 100% v out limited v ref > v mem v ref ton dly ton dly toff dly toff dly track @ 100% v trk limited v ref > v mem v ref v mem v mem v ref = 1.8v v mem = 0.9v v ref = 1.8v v mem = 1.8v ~ ~ ~ ~
zl8101 fn7832 rev 1.00 page 27 of 36 july 13, 2012 tracking with autocomp enabled the zl8101 uses a unique ramping algorithm that results in near perfect tracking while ramping. this is accomplished by deriving different compensator coefficients for ramping than those used for steady-state operation. the ramp compensation is derived from the configured rise/fall time, vin, and vout. while ramping the loop bandwidth is intentionally set to a very low value so response to transients will be limited. the user should limit dynamic loading while ramping. once the ramp has completed the autocomp algorithm will begin and a new optimized compensator solution will be found. if autocomp is disabled the controllers will switch to the co nfigured compensator by using the pid taps defined in the config uration files. if autocomp is enabled the tracking member rise /fall times might need to be adjusted slightly until the desired tracking accuracy is achieved. for the best possible tracking accuracy disable autocomp and manually assign pid coefficients in the configuration file. current sharing and tracking when the zl8101 is configured in a current sharing group and voltage tracking mode , the vtrk pin of each sharing group member must be tied together, and connected to the reference rail?s vout node, figure 23. when the auto compensation algorithm is used the soft-start values (rise/fall times) are used to calculate the loop gain used during the turn-on/turn-off ramps. if current sharing is used constrain the rise/fall time between 5ms and 10ms to ensure current sharing while ramping. configuring tracking groups in a tracking group, the rail output with highest voltage is defined as the reference device. the device(s) that track the reference is called member device(s). the reference device will control the ramp delay and ramp rate of al l tracking devices and is not placed in the tracking mode. the reference device is configured to the highest output voltage for the group and all other device(s) output voltages are meant to track and never exceed the reference device output voltage. the reference device must be configured to have a minimum time-on delay and time-on rise as shown in equation 31. this delay allows the member device(s) to prepare their control loops for tracking followin g the assertion of enable. the member device time-off delay has been redefined to describe the time that the vtrk pin will follow the reference voltage after enable is deasserted. the delay setting sets the timeout for the member?s output voltage to turnoff in the event that the reference output voltage does not achieve zero volts. the member device(s) must have a minimum time-off delay of as shown in equation 32. all of the enable pins must be connected together and driven by a single logic source or a p mbus broadcast enable command may be used. the configuration settings for figures 18 and 19 are shown below in tables 15 and 16. in each case, the reference and member rise times are set to the same value. figure 19. ratiometric tracking 0 en en 0 a. b. v ref = 1.8v v mem = 0.9v track @ 50% v out limited v ref = 1.8v v mem = 0.9v track @ 50% v trk limited v ref v ref v mem v mem toff dly toff dly ton dly ton dly v ref = 1.8v v mem = 0.9v v ref = 1.8v v mem = 0.9v ~ ~ ~ ~ ~ ~ ~ ~ figure 20. tracking current sharing rail vtrk dev_3 mem. scl rail_1 tracking reference ddc ph_1 vcc sda tracking reference dev_1 rail_2 current sharing tracking member rout cout ph_2 ph_1 vcc sync_out vcc sharing reference dev_2 sync sync_in vaux t o n _d ly (ref) = t o n _d ly (mem) + t on_rise (ref) + 5ms = t o n _d ly (mem) + 10ms (eq. 31) t off _ dly(mem) t off_ dly(ref) + t off_ fall(ref) + 5ms (eq. 32)
zl8101 fn7832 rev 1.00 page 28 of 36 july 13, 2012 voltage margining the zl8101 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. the mgn command is set by driving the mgn pin or through the i 2 c/smbus interface. the mgn pin is a ttl-compatible input that is continuously monitored and can be driven directly by a processor i/o pin or other logic-level output. the zl8101?s output will be forced higher than its nominal set point when the mgn command is set high, and the output will be forced lower than its nominal set point when the mgn command is set low. default margin limits of v nom 5% are pre-loaded in the factory, but the margin limits can be modified through the i 2 c/smbus interface to as high as v nom + 10% or as low as 0v, where v nom is the nominal output voltage set point determined by the v0 and v1 pins. a safety feature prevents the user from configuring the output voltage to exceed v nom + 10% under any conditions. the margin limits and the mgn command can both be set individually through the i 2 c/smbus interface. additionally, the transition rate between the nomi nal output voltage and either margin limit can be configured through the i 2 c interface. please refer to application note an2033 for detailed instructions on modifying the margin ing configurations. external voltage monitoring the voltage monitoring (vmon) pin is available to monitor the voltage supply for the external driver ic. if the voltage falls below a predefined threshold value (adjustable through a pmbus command), the device will fault and stop sending pwm signals. a 1/16 external resistor divider is required to keep the maximum voltage on this pin to less than 1.15v. i 2 c/smbus communications the zl8101 provides an i 2 c/smbus digital interface that enables the user to configure all aspects of the device operation as well as monitor the input and output parameters. the zl8101 can be used with any standard 2-wire i 2 c host device. in addition, the device is compatible with smbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related to continuous fault monitoring. pull-up resistors are required on the i 2 c/smbus. the zl8101 acce pts most standard pmbus commands. when controlling the device with pmbus commands, it is recommended that the en able pin is tied to sgnd. i 2 c/smbus device address selection when communicating with multiple smbus devices using the i 2 c/smbus interface, each device must have its own unique address so the host can distin guish between the devices. the device address can be set according to the pin-strap options listed in table 17. address values are right-justified. table 17. tracking mode configuration r ss (k ) uvlo (v) tracking ratio (%) upper track limit ramp-up/ramp-down behavior 19.6 4.5 100 limited by target voltage output not allowed to decrease before pg 21.5 output will always follow vtrk 23.7 limited by vtrk pin voltage output not allowed to decrease before pg 26.1 output will always follow vtrk 28.7 50 limited by target voltage output not allowed to decrease before pg 31.6 output will always follow vtrk 34.8 limited by vtrk pin voltage output not allowed to decrease before pg 38.3 output will always follow vtrk 42.2 10.8 100 limited by target voltage output not allowed to decrease before pg 46.4 output will always follow vtrk 51.1 limited by vtrk pin voltage output not allowed to decrease before pg 56.2 output will always follow vtrk 61.9 50 limited by target voltage output not allowed to decrease before pg 68.1 output will always follow vtrk 75 limited by vtrk pin voltage output not allowed to decrease before pg 82.5 output will always follow vtrk
zl8101 fn7832 rev 1.00 page 29 of 36 july 13, 2012 if additional device addresses are required, a resistor can be connected to the sa0 pin according to table 18 to provide up to 25 unique device addresses. in this case, the sa1 pin should be tied to sgnd. if more than 25 unique device addresses are required or if other smbus address values are desired, both the sa0 and sa1 pins can be configured with a resistor to sgnd according to equation 31 and table 19. using this method, the user can th eoretically configure up to 625 unique smbus addresses, howe ver the smbus is inherently limited to 128 devices so attempting to configure an address higher than 128 (0x80) will caus e the device address to repeat (i.e., attempting to configure a device address of 129 (0x81) would result in a device address of 1). therefore, the user should use index values 0-4 on the sa1 pin and the full range of index values on the sa0 pin, which will provide 125 device address combinations. note that the smbus address 0x4b is reserved for device test and cannot be used in the system. to determine the sa0 and sa1 resistor values given an smbus address (in decimal), follow step s 1 through 5 to calculate an index value and then use table 19 to select the resistor that corresponds to the calculated index value as follows: 1. calculate sa1 index: sa1 index = address (in decimal) 25 2. round the result down to the nearest whole number. 3. select the value of r1 from table 19 using the sa1 index rounded value from step 2. 4. calculate sa0 index: sa0 index = address ? (25 x sa1 index) 5. select the value of r0 from table 19 using the sa0 index value from step 4. table 18. smbus device address selection sa0 low open high sa1 low 0x20 0x21 0x22 open 0x23 0x24 0x25 high 0x26 0x27 reserved table 19. smbus address values r sa (k )smbus address 10 0x00 11 0x01 12.1 0x02 13.3 0x03 14.7 0x04 16.2 0x05 17.8 0x06 19.6 0x07 21.5 0x08 23.7 0x09 26.1 0x0a 28.7 0x0b 31.6 0x0c 34.8 0x0d 38.3 0x0e 42.2 0x0f 46.4 0x10 51.1 0x11 56.2 0x12 61.9 0x13 68.1 0x14 75 0x15 82.5 0x16 90.9 0x17 100 0x18 smbusaddress 25 sa1 ? ? index ? sa0 index ? in decimal ?? ? + = (eq. 33) table 20. smbus address index values r sa (k )sa0 or sa1 index 10 0 11 1 12.1 2 13.3 3 14.7 4 16.2 5 17.8 6 19.6 7 21.5 8 23.7 9 26.1 10 28.7 11 31.6 12 34.8 13 38.3 14 42.2 15 46.4 16 51.1 17 56.2 18 61.9 19 68.1 20 75 21 82.5 22 90.9 23 100 24
zl8101 fn7832 rev 1.00 page 30 of 36 july 13, 2012 digital-dc bus the digital-dc communications (ddc ) bus is used to communicate between zilker labs digital-dc devices. this dedicated bus provides the communication channel between devices for features such as sequencing, fault spreading, and cu rrent sharing. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bus in order to guarantee the rise time as follows: where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to vr or to an external 3.3v or 5v supply as long as this voltage is present prior to or during device power-up. as rules of thumb, each device connected to the ddc bus presents ~10pf of capacitive loading, and each inch of fr4 pcb trace introduces ~2pf. the ideal design will use a central pull-up resistor that is well-matched to the total load capacitance. in power module applications, the user should consider whether to place the pull-up resistor on the module or on the pcb of the end application. the minimum pull-up resistance should be limi ted to a value that enables any device to assert the bus to a vo ltage that will en sure a logic 0 (typically 0.8v at the device mo nitoring point) given the pull-up voltage (5v if tied to vr) and th e pull-down current capability of the zl8101 (nominally 4ma). phase spreading when multiple point of load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically. in order to enable phase spreading, all converters must be synchronized to the same switchin g clock. the pmbus is used to set the configuration of the sync pin for each device as described in ?switching frequency and pll? on page 17. selecting the phase offset for the device is accomplished by selecting a device address according to equation 35: for example: ? a device address of 0x00 or 0x20 would configure no phase offset ? a device address of 0x01 or 0x21 would configure 45 of phase offset ? a device address of 0x02 or 0x22 would configure 90 of phase offset the phase offset of each device may also be set to any value between 0 and 360 in 22 .5 increments via the i 2 c/smbus interface. refer to application note an2033 for further details. output sequencing a group of zilker labs devices may be configured to power up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. multi-device sequencing can be achieved by configuring each device through the i 2 c/smbus interface or by using zilker labs patented autonomous sequencing mode. autonomous sequencing mode configures sequencing by using events transmitted between devices over the ddc bus. the sequencing order is determined using each device?s ddc rail id number and selecting the ddc rail id# prequel and sequel for each zl controller in the sequencing group. the ddc rail id# number is automatically assigned and based on the last 5 lsb?s of the smbus address. care must be taken when configuring the address to ensure that duplicate rail id?s are not created, since they repeat for every 32 consecutive smbus addresses. if a current sharing group is part of the sequencing group use the common ishare rail id to define the prequel/sequel function. to configure autonomous sequencing mode, the i 2 c/smbus interface must be used, the sequen cing function is not available using pinstraps. the sequencing group will turn on in order starting with the 1st device (no prequel assigned) an d continue to the configured sequel and so on. when turning off, the sequencing group will reverse the startup order. the enable pins and ddcbus of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. each sequencing event is triggered by the prequel controllers power-good assertion which is then forwarded via the ddcbus. enable must be driven low to initiate a sequenced turnoff of the group. refer to application note an2033 for details on sequencing via the i 2 c/smbus interface. rise time r pu c load ? 1 ? s ? = (eq. 34) phase offset device address x 45 = (eq. 35)
zl8101 fn7832 rev 1.00 page 31 of 36 july 13, 2012 fault spreading digital dc devices can be configured to broadcast a fault event over the ddc bus to the other devices in the group. when a non-destructive fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the ddc bus. the other devices on the ddc bus will shut down together if configured to do so, and will attempt to re-start in their prescribed order if configured to do so. active current sharing paralleling multiple zl8101 devices can be used to increase the output current capability of a single power rail. by connecting the ddc pins of each device together and configuring the devices as a current sharing rail, the units w ill share the load current equally within a few percent. figure 21 shows a typical connection for three current sharing controllers. up to 7 controllers may be used in a current sharing group. the zl8101 uses a low-bandwidth, first-order digital current sharing technique to balance the unequal phase currents by aligning the load lines of member devices to the reference device. droop is used to ensure that an y phase that begins to draw a higher current then the others will quickly regulate to a lower voltage, and thereby divert current to another phase. the zl8101 controller with the lowest pmbus address becomes the reference device. the remaining devices are called members. the reference device broadcasts its current over the ddc bus. the members adjust their vout_trim parameter until current balance is achieved. figure 22 shows that, for load lines with identical slopes, the member voltage is increased towards the reference voltage if the reference controller has a higher load current, which closes the gap between the inductor currents. the relation between reference and member current and voltage is given by equation 36. where r is the value of the droop resistance the ishare_config command is used to configure the device for active current sharing. the default setting is a stand-alone non-current sharing device. a current sharing rail can be part of a sequencing group. (eq. 36) ?? member reference out member i i r v v ? ? ? ? figure 21. current sharing group zl8101 gh gl is enb is ena ddc sda scl fb zl8101 gh gl is enb is ena ddc sda scl fb driver vout vin zl8101 gh gl is enb is ena ddc sda scl fb vaux dr iver vin dri ver vin -r -r v reference v member i member i reference i out v out figure 22. active current sharing
zl8101 fn7832 rev 1.00 page 32 of 36 july 13, 2012 turn-on/off ramp behavior the zl8101 uses a unique ramping algorithm that results in near perfect current sharing while ramp ing. this is accomplished by deriving different compensator coefficients for ramping then those used for steady-state operation. the pid taps for ramps is not user configurable. the ramp compensation is calculated from the configured rise/fall time, measured vin, and target vout values. while ramping the loop bandwidth is intentionally set to a very low value so response to transients will be limited. the user should disable dynamic loading while ramping. once the ramp has completed the autocomp algo rithm will begin and a new optimized compensator solution will be found. if autocomp is disabled the controllers will switch to the configured compensator by using the pid taps defined in the configuration files. current share fault behavior faults within a current sharin g group are not broadcast to controllers within the group. if one of the controllers detects a fault that controller will cease operation. the voltage rail will operate normally until all controlle rs in the group detect a fault and the entire rail has been disabl ed. once each controller in the sharing group has faulted the group will respond according to its configured fault response. if fault spreading is enabled, the current share rail failure is not broadcast until the entire current share rail fails. once a current sharing controller has faulted the remaining members autonomously redistribute their phase relationship with respect to the sync clock. if the faulted controller was the reference phase the standing cont roller with the lowest pmbus address will become the new reference controller. phase adding/dropping the zl8101 allows multiple power converters to be connected in parallel to supply higher load cu rrents than can be obtained by using a single-phase design. in doing so, the power converter is optimized at a load current range that requires all phases to be operational. during periods of light loading, it may be beneficial to disable one or more phases in order to reduce the current drain and switching losses asso ciated with those phases, resulting in higher efficiency. the zl8101 offers the ability to add and drop phases using a simple command in response to an observed load current change, enabling the system to continuously optimize overall efficiency across a wide load range. all phases in a current share rail are considered active prior to the current sharing rail ramp to power-good. phases can be dropped after power-good is asserted. any member of the current sharing rail can be dropped. if the reference device is dropped, the remaining active device with the lowest pmbus address will become the new reference. any change to the number of members of a current sharing rail will precipitate autonomous phas e distribution within the rail where all active phases realign their phase position based on their order within the nu mber of active members. current share checklist ensure that the following layout guidelines are observed when designing current sharing rails 1. create a common sgnd plane figure 23 2. connect bypass caps and pinstrap resistors to sgnd figure 23 3. ensure that current sense nets are kelvin connected 4. ensure that each voltage fb net is kelvin connected terminate high frequency input/output caps to low-side fet source. for additional information ab out current sharing please reference an2034. monitoring via i 2 c/smbus a system controller can monitor a wide variety of different zl8101 system parameters through the i 2 c/smbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be asserted when any number of pre-configured fault conditions occur. pgnd sgnd v25 vr gpio figure 23. common sgnd plane for current sharing single point ground unification connection all current sharing controlle rs have a common sgnd plane sgnd v25 vr gpio pwmh pwml driver pwmh pwml driver sgnd vin vout figure 24. kelvin connection examples switch node direction of current flow output inductor with custom 4 pad footprint kelvin connections routed differentially averaging capacitor resistor place averaging filter close to zl_device alternate inductor footprint zl8101 isena isenb vout differential route to averaging filter place and route on same layer
zl8101 fn7832 rev 1.00 page 33 of 36 july 13, 2012 the device can also be monitored continuously for any number of power conversion parameters including but not limited to the following: ?input voltage ?output voltage ? output current ? internal junction temperature ? temperature of an external device ?switching frequency ? duty cycle the pmbus host should respond to salrt as follows: 1. zl device pulls salrt low. 2. pmbus host detects that salrt is now low, performs transmission with alert respon se address to find which zl device is pulling salrt low. 3. pmbus host talks to the zl device that has pulled salrt low. the actions that the host performs are up to the system designer. if multiple devices are faulting, salrt will still be low after doing the above steps and will require transmission with the alert response address repeatedly until all faults are cleared. please refer to application note an2033 for details on how to monitor specific parameters via the i 2 c/smbus interface. temperature monitoring using the xtemp pin the zl8101 supports measurement of an external device temperature using either a thermal diode integrated in a processor, fpga or asic, or using a discrete diode-connected 2n3904 npn transistor. illustrates the typical connections required. snapshot? parameter capture the zl8101 offers a special mechanism that enables the user to capture parametric data during normal operation or following a fault. the snapshot functionality is enabled by setting bit 1 of misc_config to 1. see an2033 ?zilker labs pmbus command set - ddc products? for details on using the snapshot feature in addition to the parameters supported. the snapshot feature enables the user to read status and parameters via a block read transfer through the smbus. this can be done during normal operation, although it should be noted that reading the 22 bytes will occupy the smbus for some time. the snapshot_control command en ables the user to store the snapshot parameters to flash memory in response to a pending fault as well as to read the stored data from flash memory after a fault has occurred. table 21 describes the usage of this command. automatic writes to flash memory following a fault are triggered when any fault threshold level is exceeded, provided that the specific fault?s response is to shut down (writing to flash memory is not allowed if the device is configured to re-try following the specific fault condition). it should also be noted that the device?s v dd voltage must be maintained during the time when the device is writing the data to flash memory; a process that requires between 700s to 1400s depending on whether th e data is set up for a block write. undesirable results may be observed if the device?s v dd supply drops below 3.0v during this process. in the event that the device experiences a fault & power is lost, the user can extract the last snapshot parameters stored during the fault by writing a 1 to snapshot_control (transfers data from flash memory to ram) and then issuing a snapshot command (reads data from ram via smbus). non-volatile memory and device security features the zl8101 has internal non-volatile memory where user configurations are stored. integr ated security measures ensure that the user can only restore the device to a level that has been made available to them. refer to ?start-up procedure? on page 16 for details on how the device loads stored values from internal memory during start-up. during the initialization process, the zl8101 checks for stored values contained in its internal non-volatile memory. the zl8101 offers two internal memory storage units that are accessible by the user as follows: 1. default store: a power supply module manufacturer may want to protect the module from damage by preventing the user from being able to modify certain va lues that are related to the physical construction of the module. in this case, the module manufacturer would use the defa ult store and would allow the user to restore the device to its default setting but would restrict the user from restoring the device to the factory settings. 2. user store: the manufacturer of a piece of equipment may want to provide the ability to modify certain power supply settings while still protecting the equipment from modifying values that can lead to a system level fault. the equipment manufacturer would use the user store to achieve this goal. please refer to application note an2033 for details on how to set specific security measures via the i 2 c/smbus interface. figure 25. xtemp pin connection zl8101 sgnd xtemp p fpga dsp asic embedde d thermal diode zl8101 sgnd xtemp q9 2n3904
zl8101 fn7832 rev 1.00 page 34 of 36 july 13, 2012 configuration files zilker labs digital-dc? devices must be configured through pin-strap settings or by using pmbus? commands. a configuration file is a human-read able text file that contains a sequence of pmbus commands to be written to a device. configuration files also aid in sharing device settings to others for additional development, troubleshooting, or manufacturing. configuration files are text files that can easily be edited using a text editor such as microsoft notepad or they can be created by the power navigator gui application. programmable gain amplifier bias current a simplified schematic for the voltage sense amplifier is shown below in figure 26. the amplifier can source a maximum of 100a when v out = 0. if the load impeda nce is high vout will begin to charge because of the bias current. to avoid any prebias condition place an a ppropriate bleed resistor across vout. if current sharing is used scale the bleed resistor by the number of current sharing controllers. figure 26. pga bias current 100a max 1.25v vsen- vsen+ + - v25 + - out pga
fn7832 rev 1.00 page 35 of 36 july 13, 2012 zl8101 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. this product is subject to a license from power on e, inc. related to digital power technology as set forth in u.s. patent no. 7,000,125 and other related patents owned by power one, inc. these license rights do not extend to stand-alone pol regulators unless a royalty is paid to power one, inc. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2011-2012. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. i products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: zl8101 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date rev. # change july 13, 2012 fn7832.1 initial release
zl8101 fn7832 rev 1.00 page 36 of 36 july 13, 2012 package outline drawing l32.5x5g 32 lead quad flat no-lead plastic package rev 0, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 17 25 24 8 1 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 3 .50 max 1.00 see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3.50 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) exp. dap index area

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